![]() The obtained results suggest that the hybrid PS/SFT structures are well-suited to superconducting computing circuits as they are built of magnetic and non-magnetic transition metals and therefore have low impedances (1-30 Ohm).Ī model of superconducting computer memory exploiting the orthogonal spin transfer (OST) in a pseudo-spin-valve (PSV) that is controlled by a three-terminal Josephson superconducting-ferromagnetic transistor (SFT) is developed. The suggested model allows studying the influence of noises, punch-through effect, crosstalk, parasitic, etc. Modeling the single MC as well as the larger MC-based circuits comprising respectively twelve and thirty elements suggest that such the memory cells can undergo ultrafast switching (sub-ns) and low energy consumption per operation (sub-100 fJ). Thus, the whole switching dynamics of MC depends on the non-equilibrium and nonstationary properties of PS and SFT. ![]() Physically, a word pulse triggers SFT to a resistive state, causing the PS switching between the logical "0" and "1" states. ![]() Elementary logical operations comprising the read/write processes occur when a word pulse applied to the SFT's injector coincides with the respective bit pulse acting on MC. Logical units "0" and "1" are associated with the two PS states respectively characterized by two different values of resistance. The memory model is formulated in terms of the equation-defined PS and SFT devices integrated into the PS/SFT memory cell (MC) circuit. The building blocks of the memory are hybrid PS and SFT structures. To illustrate the properties and use of the Qucs Verilog-A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models.Ī model of superconducting computer memory exploiting the orthogonal spin transfer (OST) in the pseudospin valve (PS) that is controlled by the three-terminal Josephson superconducting-ferromagnetic transistor (SFT) is developed. This paper introduces a new approach to the generation of Verilog-A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. In traditional circuit simulation, the generation of a Verilog-A model from a schematic, with embedded non-linear behavioural sources, is not automatic but is normally undertaken manually. Following, the standardization of Verilog-A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. The Qucs equation-defined device is an extension of the SPICE style non-linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. The current generation of SPICE-based open source general public license circuit simulators, including Qucs, Ngspice and Xyce ©, implements a range of mathematical operators and functions for modelling physical phenomena and system performance. Since the introduction of SPICE non-linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels.
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